The present invention relates to the development of semiconductor devices, and more particularly, to a method and apparatus for generating with a computer the layout of cells included in a semiconductor device.
Due to the enlargement of recent semiconductor devices (LSIs), the time for designing the semiconductor devices has become longer. To shorten the design time, the number of design processes that are redone must be reduced. Thus, the designing of a floor plan for an LSI must be optimized.
In the prior art, an LSI is designed by generating a floor plan from a netlist obtained through logic synthesizing. Cells are laid out and wires are routed according to the floor plan to generate a chip layout. Then, a circuit simulation is conducted on the chip layout. The circuit simulation verifies whether the LSI of the chip layout will function at a level that would ensure the reliability of signals and power supplies.
A typical LSI includes a plurality of standard cells and a plurality of macro cells. The generation of the LSI floor plan (layout data) includes a determination of the layout and the macro cells and standard cells. The relative positions of the macro cells and the orientation of each macro cell is determined by taking into consideration factors such as routability and timing closure (refer to Japanese Laid-Open Patent Publication No. 2004-13205). Standard cells are laid out in standard cell regions, which differ from the regions in which the macro cells are laid out.
The chip size of an LSI is determined irrelevant to the size of the macro cells. Thus, when laying out a plurality of macro cells, empty regions (overly narrow regions) may be formed between macro cells. The layout of a standard cell in an overly narrow region would produce a detour net that detours signal nets. This would affect the routability and timing closure in an undesirable manner. Therefore, when designing and LSI in the prior art, the overly narrow region is set as a dead space in which the layout of standard cells is prohibited.